1. Field of the Invention
The present invention relates to sense amplifiers for integrated circuit memory devices and, in particular, to a programmable sense amplifier which enables large voltage swings in read only memories.
2. Discussion of the Prior Art
A read only memory (ROM) is a widely used integrated circuit device for storing digital information. Data is maintained in a ROM in the form of binary "1"s and "0"s stored in memory cells located at each intersection of the ROM's row lines and column lines. Data stored in the columns of a selected row constitutes a "word". The input signal to the ROM addresses a "word" through an address decoder. The appearance of a "0" in a retrieved word causes the ROM voltage to remain high, i.e. unchanged. The appearance of a "1" in a retrieved word causes the ROM voltage to decrease. The voltage decrease is detected by the sense amplifier which then provides the ROM output.
The most popular approach to ROM sense amplifier design is to build and tune circuits that are sensitive to the minimum expected voltage swing in a given ROM. This is known as "precision tuning". The value of the minimum expected voltage swing in a ROM is inversely proportional to the number of "1"s stored in a given column of the ROM, where the maximum possible number of "1"s in the column is equal to the number of rows in the ROM. The actual load on the sense amplifier determines the values to be used in sizing the different transistors comprising the sense amplifier. These values are determined after a long, detailed simulation process utilizing computer aided design (CAD) techniques.
If there are many rows in the ROM, the worst case voltage swing will be very small. Thus, a very sensitive circuit must be designed in order to accurately sense this change.
There are several problems associated with sensitive circuits of this type. If a word in the ROM contains a "0" in one of its bits, then the voltage level of this bit line when this word is chosen must remain "HIGH". If noise from other bit lines that are discharged at this time, or from power lines, is introduced into this bit line through parasitic coupling capacitors, the sense amplifier that is connected to this bit line might sense it and produce a wrong output. Since it is extremely difficult to predict and model the noise to be expected in a particular ROM and sense amplifier layout, the design of noise-immune, sensitive sense amplifiers is correspondingly difficult.
Also, the voltage swing itself may be smaller than expected due to process variables. For example, the diffusion capacitance can be higher than expected due to fluctuations in the implant step in the fabrication of the device. Similarly, the drive capability of the discharging transistors that comprise the "1"s in the ROM locations may be smaller than expected. This can result from a wide variety of causes, such as changes in transistor threshold voltage, mobility reduction and temperature effects.
Because of these unpredictable problems, even after many CAD iterations, the manufactured sense amplifier circuit design might not work in a particular application. If the problem is noise, an additional tuning step is required. If the problem is a smaller than expected voltage swing, then a larger discharge time will be required for the transistor to produce the desired voltage swing; this results in frequency reduction. In both cases, if the ROM must operate within a given frequency, a redesign of the device is required with no guarantee that the redesign will operate within a desired specification.
For the reasons stated above, sense amplifier design is known to present one of the most complicated and problematic elements of memory design.